MIPS Assembly Pipelined Processor

MIPS Pipelined Processor on Basys3 FPGA

A Verilog implementation of a classic five-stage pipelined MIPS processor deployed on a Basys3 FPGA board, built as part of CS224.

Pipeline Stages — Fetch, Decode, Execute, Memory, and Writeback, connected through five pipeline registers (PipeWtoF, PipeFtoD, PipeDtoE, PipeEtoM, PipeMtoW).

Hazard Detection — A dedicated HazardUnit handles data forwarding from M and W stages back to E, load-use stalls, and branch stalls to prevent misprediction.

Instruction Set — Supports R-type (ADD, SUB, AND, OR, SLT) and I-type (LW, SW, ADDI, BEQ) instructions, plus a custom Rotate Left (ROL) instruction implemented via a leftrotate module using (a << shamt) | (a >> (32 - shamt)).

Display — A 7-segment controller shows the PC on the rightmost digits and the ALU result on the leftmost, with LEDs indicating control signal states (memory write, register write, rotate flag).